In this role you will
Be responsible for SOC Functional verification and sign-off.
Help define a comprehensive verification methodology for SOCs.
Test plan development, coverage goals, simulation performance enhancements and regression methodology using Verilog, System Verilog, UVM, C/C++, Perl/Python.
Evaluate tradeoffs between block vs full chip verification scope with directed vs constrained random tests to define verification test bench boundaries.
Develop system level verification strategy.
Develop highly reusable system level test plan content and execute the content.
Architect the reusable and scalable test bench.
Integrate VIPs for AHB/APB/I3C/SPI/UART/JTAG/etc.
Integrate VIPs for PCIE/AXI and build system stimulus on top of VIP stimulus library.
Integrate DIMM model and work with designers
on phy bring up and implement complex address
translation functions.
Develop VIPs for complex proprietary protocols.
Execute coverage for verification closure, conduct reviews.
Develop and maintain regressions, tools, infrastructure.
Measure performance and work with architects and designers to meet the spec.
Write verification firmware, bring up real firmware.
Functional bring up and debug support on FPGA/emulation platform.
Work with Architects and Designers to deliver bug free SOC.
Close the full verification cycle of block/subsystem/full chip/multi chip.
Support post-silicon bring up.
We are looking for
Passionate about solving complex problems through highly independent hands-on work with cutting-edge verification tools, flows and methodologies.
Experience in creating verification environment from scratch for IP/SubSystem/SOC using Verilog, System Verilog, UVM, C/C++, perl, Python.
Proven experience in full chip verification from the plan development to tape-out sign-off.
Strong written and verbal communication skills for strong collaboration with verification, design, architecture teams.
It is big plus if you have experience with emulation tools like Veloce, Cadence Palladiuma
Experience in verifying system architecture including Memory subsystems , IO peripherals (SPI/UART/I3C/JTAG), bus protocols (AXI/APB/AHB), PCIE, PHY, NOC, interconnects, Fabrics, RISC-V based designs, CPU clusters, accelerators.
Experience in leadership and mentoring team members.
It is a big plus if you have:
- Experience with formal verification
- Experience with PCIe 4, 5 or 6
- CXL, UCIe and general fast interconnection protocols. For verification PHY layera, and PIPE-a and transaction layera.
- 5nm and beyond STA expert with physical design and synthesis (frontend) experience (SDC and time closure).
