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Data Science Opportunity:

Are you a passionate data scientist interested in diving deeper into esports? Are you curious to know which team is ruling the game and whether the worst-performing team in Asia can outshine the best-performing team in North America? Do you have a burning desire to explore whether supports are better than mid-players? If yes, then we have an exciting opportunity for you!

Join us as our Data Scientist and be part of our mission to create objective rankings of teams and players across multiple esports. We are seeking a dynamic commander who can take charge of this exciting project and help us uncover the answers to these intriguing questions (and many more!) for everyone interested in esports. As the ideal candidate, you should have a solid background in machine learning methods and a strong inclination towards self-starting. We are counting on you to guide us in the most efficient way to unravel these mysteries, taking charge of this project while getting stakeholder buy-in across the company.

This temporary full-time role is available from January to September 2024.

What You’ll Be Doing:

Collect and aggregate data from internal and external databases
Preprocess structured and unstructured data
Preprocess structured and unstructured data
Work closely with internal and external parties to define key data
Examine large amounts of data to detect patterns for ranking
Develop algorithms for ranking esports players and teams
Present results to stakeholders, including those with limited technical knowledge
Partner with design to display rankings in the best way possible

What You’ll Need:

• 2+ years of Data Science experience
• Proficient in Python
• Ability to write SQL queries
• Familiarity with APIs
• In-depth knowledge of statistical analysis and machine learning methods
• Experience with data wrangling and handling data imperfections
• Hands-on experience with data science tools
• Problem-solving and detail-oriented mindset with strong business sense.

ABOUT YOU 

Smart and creative self-starter with excellent communication skills along with a passion for solving complex problems and capable of working across teams transparently. You should have a strong background in applying and using machine learning models, data structures, scripting in Bash shell, Python PowerShell or other relevant scripting languages to accelerate automation.  Exposure to computer architecture, operating systems internals, statistics, and mathematics is very relevant. The candidate should also have a solid understanding of SW quality and processes. 

KEY RESPONSIBILITIES 

• Participate in product and software requirement reviews with engineering teams. 
• Design, develop, execute, and maintain tests for inference and machine learning software stack based on product requirements and microarchitectural specs.  
• Develop and craft test plans based on microarchitectural specifications. Drive test plan reviews with software engineering teams. 
• Monitor inference and training performance and power consumption across stack versions and hardware IPs by defining and tracking verification metrics. 
• Research verification methodologies to improve automation, productivity, and efficiency. 
• Collaborate with teams across multiple geographic locations. 
• Work in multiple environments which involves Hypervisors, Containers, Linux, Windows  
• Develop and deliver training materials on new features and test methodologies. 
• Stay abreast of the latest AI technologies, emerging tools, and industry best practices. 

PREFERRED EXPERIENCE & SKILLS 

• Strong Computer Science fundamentals and problem-solving skills 
• Strong programming skills in at least two of the following scripting languages: Python, Javascript, Bash, PowerShell 
• Strong understanding of applied machine learning using current ML Frameworks: Pytorch, Tensorflow, ONNX, CNTK, R, etc.; Exposure to C/C++, Go, Rust a plus 
• Good understanding of multi-core compute hardware and device driver fundamentals 
• Good knowledge of computer virtualization technologies: Hyper-V, KVM, LXC, Docker, K8, etc. 
• Good knowledge and experience working with OS SDK/developer tools in Linux, Windows 
• 4+ years of relevant experience 

ABOUT OPCOM

Opcom GmbH is a software services provider that is dedicated to delivering expert solutions to our clients. Founded 2010 in Switzerland, successfully operating across the world as a leading consulting and technology services provider. We strive to contribute our expertise and build valuable relationships to bring our client's visions, projects, and rights to life. Join us to grow together.

The role:

In this position, you will perform Functional Verification of next generation high performance Microprocessor designs – with a focus on leveraging Emulation environments.

The person:

We are searching for candidates who love technical challenges and are natural problem solvers. Detail oriented people who seek continuous improvement and thrive in an innovative environment are encouraged to apply.

Key Responsibilities:

• Develop and run tools, infrastructure, processes and flows to enable functional verification in the emulation environment
• Develop emulation testbench components to stimulate and monitor the Device-Under-Test
• Maintain and improve emulation infrastructure and methodology.
• Develop and execute on verification test plans in emulation environments
• Develop, simulate and debug directed and random stimulus to find bugs in the microprocessor design and verify the functionality and verify conformance to the ISA and other specifications
• Work with RTL designers to resolve failures and discrepancies
• When presented with Silicon issues, replicate in the emulation environment, and provide debug expertise to root cause the issue and ensure complete validation
• Contribute towards and drive as needed pre-silicon and/or post-silicon verification of complex architectural and microarchitectural features
• Document test plans and testbench component plans and drive reviews with peers and partners

Preferred experience:

We are looking for design verification experience with a background in Emulation. Other skills include: 

• Hardware Verification methodology and techniques such as emulation, assertions simulation, debug, coverage
• Emulator experience (e.g. Palladium, Veloce, ZeBu, HAPS)
• Debug tools or waveform viewers.
• Hands-on work in Verilog or System Verilog programming for either hardware modeling or testbench development or projects of similar scope and complexity
• Experience with industry standard verification testbench and IP methodology
• Scripting languages (e.g. Perl or Python or Ruby)
• CPU/GPU architecture knowledge is a plus
• Assembly language programming and Instruction Set Architecture knowledge is a plus

Academic credentials:

• MSEE, MSCE or related degree plus relevant years of experience

The Role:

Low Power Advanced Development team is seeking talented, self-motivated individuals to help develop low power innovations that enable industry-leading power efficient computing and graphics products. We have openings for R&D engineers to serve as key contributors in small project teams working on low power advanced development projects. 

The Person:

A candidate who is seeking challenging projects in low power design using the latest modern semiconductor technologies, who is eager to learn and is a good team player.

Key Responsibilities:

• Working on low power circuit design for CPU and/or GPU applications, custom mixed-signal circuits and logic design in advanced CMOS technologies using custom and semi-custom physical design flows
• Design, simulate, and verify analog, high speed digital, and mixed-signal circuits
• Design for optimum power/speed/area efficiency
• Closely work with and supervise layout/mask designers by providing annotated schematics, floor plans, layout, reliability and manufacturability design guidelines
• Experience in back-end design verification tools and flows including debugging LVS and DRC issues in collaboration with the layout team
• Work in collaboration with Physical Design Engineers in chip level planning and integrations
• Create or in collaboration with other team members design reviews, technical reports, and other documentation required for meeting the design quality and for the tapeout signoff

Preferred Experience:

• Requires strong understanding of analog/mixed signal design concepts and CMOS processes
• Experience in Phase-Locked Loop (PLL) design, Frequency-Locked Loop (FLL) design, Oscillators, High Speed Clock circuits, Linear and Switching voltage regulators, DAC, voltage comparators
• Knowledge in ADC design is a plus
• Cadence's custom IC design environment with special emphasis on Virtuoso schematic/layout design entry tools
• Synopsys Custom Designer schematic/layout design entry tool experience is a plus
• Analog/mixed signal circuit simulators, specifically Hspice, Spectre, SpectreRF
• Design automation (scripting, python, perl, csh)
• Verilog-A modelling
• Matlab
• Knowledge in the digital design flows including Verilog HDL is a plus
• Strong communication skills, teamwork experience and a quick learner in a fast-moving environment

In this role you will

Be responsible for SOC Functional verification and sign-off.
Help define a comprehensive verification methodology for SOCs.
Test plan development, coverage goals, simulation performance enhancements and regression methodology using Verilog, System Verilog, UVM, C/C++, Perl/Python.
Evaluate tradeoffs between block vs full chip verification scope with directed vs constrained random tests to define verification test bench boundaries.
Develop system level verification strategy.
Develop highly reusable system level test plan content and execute the content.
Architect the reusable and scalable test bench.
Integrate VIPs for AHB/APB/I3C/SPI/UART/JTAG/etc.
Integrate VIPs for PCIE/AXI and build system stimulus on top of VIP stimulus library.
Integrate DIMM model and work with designers
on phy bring up and implement complex address
translation functions.
Develop VIPs for complex proprietary protocols.
Execute coverage for verification closure, conduct reviews.
Develop and maintain regressions, tools, infrastructure.
Measure performance and work with architects and designers to meet the spec.
Write verification firmware, bring up real firmware.
Functional bring up and debug support on FPGA/emulation platform.
Work with Architects and Designers to deliver bug free SOC.
Close the full verification cycle of block/subsystem/full chip/multi chip.
Support post-silicon bring up.

We are looking for

Passionate about solving complex problems through highly independent hands-on work with cutting-edge verification tools, flows and methodologies.
Experience in creating verification environment from scratch for IP/SubSystem/SOC using Verilog, System Verilog, UVM, C/C++, perl, Python.
Proven experience in full chip verification from the plan development to tape-out sign-off.
Strong written and verbal communication skills for strong collaboration with verification, design, architecture teams.
It is big plus if you have experience with emulation tools like Veloce, Cadence Palladiuma
Experience in verifying system architecture including Memory subsystems , IO peripherals (SPI/UART/I3C/JTAG), bus protocols (AXI/APB/AHB), PCIE, PHY, NOC, interconnects, Fabrics, RISC-V based designs, CPU clusters, accelerators.
Experience in leadership and mentoring team members.

It is a big plus if you have:

• Experience with formal verification
• Experience with PCIe 4, 5 or 6
• CXL, UCIe and general fast interconnection protocols. For verification PHY layera, and PIPE-a and transaction layera.
• 5nm and beyond STA expert with physical design and synthesis (frontend) experience (SDC and time closure).